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PLL650-01
Low EMI Network LAN Clock
FEATURES
* * * * * * * * * * Full CMOS output swing with 25 mA output drive capability at TTL levels. Advanced, low power, sub-micron CMOS process. 25.0MHz fundamental crystal or reference clock signal. Six output clocks with selectable frequencies. SDRAM frequencies of 67,83,100, and 133MHz. Spread Spectrum Technology selectable for EMI Reduction from 0.25% to 0.5% center. Buffered crystal reference output. Ideal for Network switches. 3.3V operation. Available in 150mil 20-Pin SSOP.
PIN CONFIGURATION
FS0 XOUT XIN VDD FS1 GND CLKC1 CLKC2 CLKB2 CLKB1
1 2 3
20 19 18
FS3 FS2 REF/CS1*^ CLKA1 VDD OE^ GND CLKA2 FS4 CS0
PLL 650-01
4 5 6 7 8 9 10
17 16 15 14 13 12 11
DESCRIPTION
The PLL650-01 is a low cost, low jitter, high performance clock synthesizer. With PhaseLink's proprietary analog Phase Locked Loop techniques, the chip accepts 25.0MHz from a crystal or a reference clock, and produces multiple outputs clocks for network chips, PCI devices, SDRAM, and ASICs.
Note: ^: 100k internal pull-up. *: Bi-directional pin. The value of CS1 is latched upon power-up. When no external pull-down resistor is connected to the pin, the internal pull-up results in a default high value for CS1. An external 10k pull-down resistor is recommended to set CS1 to low.
BLOCK DIAGRAM
OE XIN XOUT
XTAL OSC
REFOUT CLKA1 CLKA2
FS (0:4)
Control Logic
CS (0:1)
CLKB1 CLKB2 CLKC1 CLKC2
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1
PLL650-01
Low EMI Network LAN Clock
PIN DESCRIPTIONS
Name
CLKA1 CLKA2 CLKB1 CLKB2 CLKC1 CLKC2 XIN XOUT FS2 FS3 CS0 FS0 FS1 FS4 OE REF/CS1 VDD GND
Number
17 13 10 9 7 8 3 2 19 20 11 1 5 12 15 18 4,16 6,14
Type
O O O O O O I O I I I I I I I B P P
Description
Clock A Output. Frequency Select pin selectable via (FS0 ~ FS4). Clock A Output. Frequency Select pin selectable via (FS0 ~ FS4). Clock B Output. Frequency Select pin selectable via (FS0 ~ FS4). Clock B Output. Frequency Select pin selectable via (FS0 ~ FS4). Clock C Output. Selectable from jumper CS0 and table CS1 output. Clock C Output. Selectable from jumper CS0 and table CS1 output. Crystal input to be connected to a fundamental crystal or clock input. Crystal Connection. Frequency Select 2. Select outputs per table on page 3. Frequency Select 3. Select outputs per table on page 3. Clock C select pin. Select outputs for CLKC1, CLKC2. Frequency Select 0. Select outputs per table on page 3. Frequency Select 1. Select outputs per table on page 3. Frequency Select 4. Select outputs per table on page 3. Output Enable. When low, Tri-states all outputs. Buffered Reference Clock Outputs. Same frequency as crystal or clock input. This pin latches CS1 value at power up and select outputs for CLKC1, CLKC2 (See table on page 3). Has internal pull-up resistor. 3.3V power supply. Ground.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 2
PLL650-01
Low EMI Network LAN Clock
FREQUENCY (MHz) SELECTION TABLE (For a 25MHz Crystal or Clock Input)
FS0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FS1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
FS2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
FS3
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
FS4
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
CLKA1
100.0 100.0 100.0 100.0 75.0 75.0 75.0 66.667 33.333 33.333 33.333 33.333 66.667 66.667 66.667 66.667 100.0 100.0 133.333 133.333 133.333 133.333 133.333 100.0 100.0 125.0 83.333 125.0 Test 100.0 125.0 133.333
CLKA2
OFF OFF OFF OFF OFF OFF OFF OFF 16.667 16.667 16.667 16.667 33.333 33.333 33.333 33.333 OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF Test OFF OFF OFF
CLKB1
66.667 100.0 83.333 133.333 66.667 100.0 83.333 133.333 66.667 100.0 83.333 133.333 66.667 100.0 83.333 133.333 OFF OFF OFF OFF 66.667 66.667 66.667 100.0 100.0 OFF 83.333 OFF Test 100.0 OFF 133.333
CLKB2
33.333 50.0 41.667 66.667 33.333 50.0 41.667 66.667 33.333 50.0 41.667 66.667 33.333 50.0 41.667 66.667 OFF OFF OFF OFF 33.333 33.333 33.333 50.0 OFF OFF OFF OFF Test OFF OFF OFF
SST*
OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF 0.25% 0.5% 0.25% 0.5% 0.25% 0.5% OFF 0.25% OFF 0.25% 0.5% OFF Test 0.25% 0.5% 0.25%
Note: SST = Spread Spectrum Technology for EMI Reduction
CS1
0 0 1 1
CS0
0 1 0 1
CLKC1 125.0 75.0 125.0 100.0
CLKC2 125.0 75.0 50.0 OFF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 3
PLL650-01
Low EMI Network LAN Clock
FUNCTIONAL DESCRIPTION Selectable spread spectrum and output frequencies
The PLL650-01 provides selectable spread spectrum modulation and selectable output frequencies, as well as an "output enable" selection input (pin 15). Selection is made by connecting specific pins to a logical "zero" or "one", according to the frequency selection tables shown on page 3. In order to reduce the number of pins on the chip, the PLL650-01 uses pin 18 (REF/CS1) as a bi-directional pin that serves as input (CS1) upon power-up, and as output (REF) as soon as the input has been latched. Pins 1 (FS0), 5 (FS1), 19 (FS2), 20 (FS3), and 12 (FS4) are used as inputs to select the CLKA1, CLKA2, CLKB1, CLKB2 output frequencies and spread spectrum (SST) modulations (as detailed in the frequency selection table on page 3). Pins 11 (CS0) and 18 (REF/CS1) are used to select the CLKC1 and CLKC2 frequency outputs. As said above, pin 18 is a bi-directional pin. Pin 15 (OE) is the output enable selection input that tri-states (disables) all outputs when selected to "low" (logical "zero").
Connecting a selection pin to a logical "one"
In order to connect pins 1 (FS0), 5 (FS1), 19 (FS2), 20 (FS3), and 12 (FS4) to "high" (logical "one), the pins simply need to be connected to VDD. Pins 15 and 18 have an internal pull-up resistor of 100k. This internal pull-up resistor will pull the input value to a logical "one" (pull-up) by default, i.e. when no resistive load is connected between the pin and GND. For pins 15 and 18, no external pull-up resistor is therefore required for connecting a logical "one" upon. Note: since pin18 also is used as an output, it may happen that the output load present a low impedance in comparison to the internal pull-up resistor. In this case, the internal pull-up resistor may not be sufficient to pull the input up to a logical "one", and an external pull-up resistor may be required.
Connecting a selection pin to a logical "zero"
Except for pin 18 (REF/CS1) that is bi-directional, all other input pins are input only. In order to connect them to a logical "zero", the pins simply need to be grounded. Connecting pin 18 to a logical "zero" will however require the use of an external loading resistor between the pin and GND that has to be sufficiently small (compared to the internal pull-up resistor) so that the pin voltage be pulled below 0.8V (logical "zero"). In order to avoid loading effects when the pin serves as output, the value of the external pull-down resistor should however be kept as large as possible. In general, it is recommended to use an external resistor of around 10k (see Application Diagram). Note: when the output is used to drive a load presenting an small resistance between the output pin and VDD, this resistance is in essence connected in parallel to the internal pull-up resistor. In such a case, the external pull-down resistor may have to be dimensioned smaller to guarantee that the pin voltage will be low enough to achieve the desired logical "zero". This is particularly true when driving 74FXX TTL components.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 4
PLL650-01
Low EMI Network LAN Clock
APPLICATION DIAGRAM FOR SETTING CS1 (PIN 18)
Internal to chip VDD
External Circuitry
Rup Power Up Reset
R RB
Output
EN
REF/CS1
Clock Load
Latched Input
Latch
10k
Jumper options
NOTE: Rup=100k . R starts from 1 to 0 while RB starts from 0 to 1.
Electrical Specifications
1. Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model
SYMBOL
VDD VI VO TS TA TJ
MIN.
-0.5 -0.5 -65 -40
MAX.
4.6 VDD+0.5 VDD+0.5 150 85 125 260 2
UNITS
V V V C C C C kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 5
PLL650-01
Low EMI Network LAN Clock
2. AC Specifications PARAMETERS
Input Frequency Output Rise Time Output Fall Time Duty Cycle Max. Absolute Jitter Max. Jitter, cycle to cycle 0.8V to 2.0V with no load 2.0V to 0.8V with no load At VDD/2 Short term 45 50 150 80
CONDITIONS
MIN.
10
TYP.
12.5 or 25
MAX.
27 1.5 1.5 60
UNITS
MHz ns ns % ps ps
3. DC Specifications PARAMETERS
Operating Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output High Voltage At CMOS Level Operating Supply Current Short-circuit Current Internal pull-up resistor
SYMBOL
VDD VIH VIL VIH VIL VIH VIL VOH VOL VOH IDD IS Rup
CONDITIONS
MIN.
2.97
TYP.
VDD /2 VDD /2
MAX.
3.63 VDD /2 - 1 0.5
UNITS
V V V V V V V V V V
For all Tri-level input For all Tri-level input For all normal input For all normal input IOH = -25mA IOL = 25mA IOH = -8mA No Load
VDD -0.5 2 0.8 2.4 0.4 VDD -0.4 35 50
mA mA k
OE, CS1
100
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 6
PLL650-01
Low EMI Network LAN Clock
PACKAGE INFORMATION
20 PIN Narrow SSOP (inches)
SSOP Symbol A A1 B C D E H L e Min. 0.053 0.004 0.008 0.007 0.337 0.150 0.228 0.016 Max. 0.069 0.010 0.012 0.010 0.344 0.157 0.244 0.050 0.025 BSC A1 B C L e A D 450 E H
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following: Device number, Package type and Operating temperature range
PLL650-01 X C
PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRAL PACKAGE TYPE X=SSOP
Order Number PLL650-01XC-R PLL650-01XC
Marking P650-01XC P650-01XC
Package Option SSOP - Tape and Reel SSOP - Tube
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 7

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